A Phase Locked Loop (PLL) is widely applied in a System on Chip (SOC) to constitute a frequency synthesizer, a clock generator and the like. FIG. 1 is a basic structure of a PLL, in which a Phase Frequency Detector (PFD) 10 detects a frequency difference and a phase difference between an input signal Fref and a feedback signal Ffb, and generates pulse control signals UP and DN and sends them to a Charge Pump (CP) 20. In the CP 20, the pulse control signals UP and DN are converted into a current IP so as to charge or discharge a capacitor CP in a Loop Filter (LP) 30, the LP 30 generates and sends a control voltage Vctrl to a Voltage Control Oscillator (VCO) 40. The VCO 40 increases an oscillation frequency as the control voltage Vctrl is boosted, and the VCO 40 decreases the oscillation frequency as the control voltage Vctrl is dropped. An output signal Fout of the VCO 40 results in the feedback signal Ffb via a divider 50, so that the entire system forms a feedback system, and the frequency and phase of the output signal Fout are locked to a fixed frequency and phase.
A loop damping factor ξ of the PLL illustrated in FIG. 1 is denoted by Equation (1) and a loop bandwidth ωn is denoted by Equation (2):
                    ξ        =                                            R              p                        2                    ⁢                                                                      I                  p                                ⁢                                  K                  v                                ⁢                                  C                  p                                            N                                                          (        1        )                                          ω          n                =                                                            K                v                            ⁢                              I                p                                                    NC              p                                                          (        2        )            where CP denotes the capacitor of the LF 30, RP denotes a resistor of the LF 30, IP denotes a current for charging or discharging the capacitor CP (that is, the charging or discharging current output from the CP 20), Kv denotes a gain of the VCO 40, and N denotes a frequency division factor of the divider 50.
A high performance PLL should have advantages as follows: insusceptibility to variations of process, voltage and temperature (PVT), a wide frequency band, a low phase jitter and a small frequency change after being locked, a monolithic integrated filter, low power consumption for circuit and the like. However, it may be difficult to design a PLL satisfying all the requirements. A conventional PLL based on a VCO has a phase jitter caused by the noise of a power source and a substrate. The loop acts as a low-pass filter for the noise, and the narrower the loop bandwidth is, the lower the jitter will be. On the other hand, the capacitor of the filter can not be manufactured largely in size due to the requirement of monolithic integration, and at the same time, the bandwidth may be restricted by the loop stability condition. These restrictive conditions may result in the designed PLL with a narrow operation band and poor jitter performance.
A method for improving a bandwidth and lowering a jitter is to vary the bandwidth of the PLL to follow the operation frequency of the PLL. The loop has a narrow bandwidth and a low jitter in each operation status, but the varying bandwidth of the PLL may result in a very wide frequency range while reducing phase and frequency jitters introduced by the noise. An example of the method is a self-biased method to design a PLL with a loop damping factor ξ of a fixed value (typically 1). The damping factor ξ and the ratio of the loop width ωn to an angular frequency of an input signal ωref (hereinafter, referred to as an input frequency, ωref=2πFref, where Fref denotes a frequency of the input signal) are determined only by a relative value of a capacitor during a fabrication process.
The technical document titled “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques” (John G Maneatis, IEEE Journal OF Solid-State Circuits, VOL. 31, NO. 11, NOVEMBER 1996) discloses a basic structure of a self-biased PLL. As illustrated in FIG. 2, a capacitor C1 and a bias generator 60 constitute a LF 31, that is, the bias generator 60 creates a resistor of the LF 31, and a current output from an additional CP 21 is applied at the output terminal of a bias voltage VBP of the bias generator 60, so that a CP 20 charges and discharges the capacitor C1 and the CP 21 charges and discharges the resistor created by the bias generator 60.
The bias generator 60 generates bias voltages VBP and VPN from a control voltage VCTRL to provide input voltages to a VCO 41. As illustrated in FIG. 3, the bias generator 60 includes a bias initialization circuit 601, an amplifier bias circuit 602, a differential amplifier circuit 603, a half-buffer replication circuit 604 and a control voltage buffer circuit 605. The amplifier bias circuit 602 provides the differential amplifier circuit 603 with a bias, and the differential amplifier circuit 603 adjusts the bias voltage VBN, so that the half-buffer replication circuit 604 and the control voltage buffer circuit 605 replicate the control voltage VCTRL to the bias voltage VBP at the output terminal, that is, VBP=VCTRL.
The VCO 41 includes n (n≧3) differential buffer delay stages with symmetric loads, for example, the VCO 41 including three differential buffer delay stages 410 with symmetric loads as illustrated in FIG. 4. The bias voltage VBN provides the symmetric loads 411 and 412 with a bias current 2ID (ID denotes a current flowing through the symmetric load 411 or 412). The bias voltage VBP of the symmetric loads 411 and 412 equals to the control voltage VCTRL, and an equivalent resistance of the symmetric loads 411 and 412 equals to ½ gm, where gm denotes a transconductance of one transistor in the symmetric loads. A resistance of the symmetric loads 411 and 412, a time delay of the buffer stages and a frequency of the output signal (CK+ or CK−) of the VCO 41 change with the variation of the control voltage VCTRL.
It is assumed that the current IP output from the CPs 20 and 21 is x times than the bias current 2ID of the VCO 41, that is, IP=x·2ID, and the resistance RP of the LF 31 created by the symmetric load 606 in the bias generator 60 is y times than an equivalent resistance Ro of the buffer stages 410 of the VCO 41, that is, Rp=yRo=y/2 gm. Therefore, a loop damping factor ξ of the self-biased PLL illustrated in FIG. 2 is denoted by Equation (3) and the ratio of an loop bandwidth ωn to an input frequency ωref is denoted by Equation (4):
                    ξ        =                              y            4                    ⁢                                    x              N                                ⁢                                                    C                1                                            C                B                                                                        (        3        )                                                      ω            n                                ω            ref                          =                              xN                          2              ⁢                                                          ⁢              π                                ⁢                                                    C                B                                            C                                  1                  ⁢                                                                                                                                                (        4        )            where CB denotes a parasitic capacitor of the VCO 41. Thus, parameters x and y and the frequency division factor N may satisfy a certain ratio relationship through a circuit design so as to counteract the frequency division factor N, so that the damping factor ξ of the PLL and the ratio ωn/ωref of the loop bandwidth to the input frequency only depends on a relative value of the capacitors CB and C1 in a fabrication process.
Based on the above structure of the self-biased PLL, John G. Maneatis et. al. propose a self-biased PLL (see, “Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 11, NOVEMBER 2003) in which the parameters x and y in the formulas 3) and 4) are obtained. Moreover, this document also discloses that two NMOS transistors are added between the differential buffer delay stages with symmetric load in the VCO so as to clamp the phase difference between two output signals to be 180° and ensure that the VCO is able to oscillate (see, page 1801 and FIG. 11).
Compared with a basic PLL, the existing self-biased PLL has the following differences.
1. Two charge pumps are used to discharge and charge the capacitor and the resistor, while in the basic PLL only one charge pump is used.
2. The VCO includes differential buffer delay stages with symmetric loads, while in VCO of the basic PLL, the ring oscillator such as the differential ring oscillator is used. Thus, the NMOS transistor between the differential buffer delay stages with symmetric load may affect the frequency of the output signal from the VCO.
3. A bias generator is added to generate the bias voltage from the control voltage so as to provide the input voltage of the VCO. The circuit structure of the bias generator is complex.
Therefore, in order to meet the requirement that the damping factor of the loop needs to be kept as a fixed value, a large modification is made to the basic PLL to construct the existing self-biased PLL and the structure of the existing self-biased PLL is complex.